谭公之45nm cmos process 读后感

今天读了一篇论文是讨论analog/RF design challenge below 45nm cmos..it seems shrink cmos introduces extremely design challenge on analog/RF. As the process shrink below 45nm, 1) gate leakage is significant 2)output conductance reduces as process shrink... design implication on gate leakage maybe on limited used of cmos capacitance when usable frequency increases. usable frequency defined the minimum frequency where input impedence may seems to be resistive instead of capacitive. It will give design challenge on integrator circuit and hold cicuit as hold time is proportional capacitance. Second, gate leakage implication can be the drain current mismatch which no good for current mirror design... The future transistor which is FDSOI may able to resolve this problem instead of the convention planer bulk transistor..看来我需要在这方面看看有什么机会可以搞搞得。。哈哈！